The present invention relates to a semiconductor memory and particularly to a semiconductor multilevel memory having multiple storage levels of information per memory unit even under a low power supply voltage and which consumes less electrical power.
A semiconductor memories having a higher integration density, represented by a dynamic random access memory (hereinafter abbreviated as DRAM), have been developed year after year and a memory unit of semiconductor memory (hereinafter referred to as memory cell) and peripheral circuits are more and more superminiaturized. However, improvement in integration density by such superminiaturization must usually be accompanied by a large stride of advancement of element process technology such as photolithography etching, etc. and therefore a certain period is usually required for development of element process technology.
Meanwhile, demands for a very high density semiconductor memory are increasing continuously and for example, a semiconductor memory having a large capacity and less power consumption is craved for newly developed field such as a small size office computer and the terminals thereof which have recently showed fantastic growth. Namely, existing semiconductor memories are not only insufficient from the point of view of integration density but also from the point of view of power consumption and other performances.
In order to meet such requirements, a memory having a multiple level storage structure (MLS memory) is considered as an effective means for realizing a semiconductor memory having a higher integration density by the current process technology. This memory is intended to substantially increase integration density by causing a single memory cell to store the data of more than two (2) levels.
As an MLS memory, a charge transfer device (hereinafter referred to as CTD) is well known. These are explained in detail, for example, in L. Terman et al. IEEE Journal of Solid-State Circuits. Vol. sc-16, No. 5, pp. 472-478, October 1981. and M. Yamada et al. Proceedings of the 9th Conference on Solid-State Devices, Tokyo 1977, pp. 263-268, issued on January 1978.
However, the MLS memory using CTD is not yet often put into practical use, because the number of levels cannot be increased sufficiently to prevent the situation that multilevel data of an analog signal is substantially attenuated due to finite transfer efficiency peculiar to the CTD. Or, such multilevel memory is inferior because it is necessary to raise a driving pulse voltage in order to increase the transfer efficiency and such an element intrinsically has a high capacitance load and consumes a very high electrical power. Moreover, it is also inferior in such a point that a memory cell can be formed to be small because high precision A/D, D/A converters are required for loops of each CTD but integration density cannot be raised due to the restriction on the peripheral circuits.